Current mode logic (CML) circuits are often used to implement high speed serial digital communications applications. Such circuits typically use resistively-loaded differential switch arrangements which can provide high speed, low supply noise generation, and high supply noise immunity. However, CML circuits draw relatively high power and may have limited speed in a given process technology.
One specific example of a high speed digital circuit is a crosspoint switch, which can selectably connect data signals between multiple inputs and multiple outputs. FIG. 1 shows the functional block architecture of a typical crosspoint switch. The left edge of the figure shows inputs 0–39 and the bottom edge shows outputs 0–35. Any input can be connected to any number of outputs. Each of the smaller dashed line boxes along the left side of FIG. 1 represents a two-stage input buffer. The larger dashed line boxes in the center of the figure are arrays of point cells to connect a selected input to a selected output. The smaller dashed line boxes along the bottom side of the figure are two-stage multiplexers to selectably connect multiple data paths to a given output port via an output buffer stage. As shown in FIG. 1, each of the second stage input buffers and first stage output multiplexers may serve only a subset of the output and input ports respectively. In addition, at high data speeds above 1 Gb/sec, the crosspoint may be further timesliced using parallel paths into alternating data slices at half the data rate each.
FIG. 2 provides a slice of such a crosspoint switch showing a single path connecting one input port to one output port. The crosspoint switch can be conceptually divided into a high-speed data path (shown by thin lines in FIG. 2) and a lower-speed control plane that determines connectivity (shown by thick lines in FIG. 2). The control plane is run by a digital clocking signal and determines which pieces of the data path should be enabled for a given connectivity and when the enabling signals should change. For the switch control plane, connectivity data to control the data path may be written into control latches or flip-flops.
In FIG. 2, the first stage buffer 21 provides a high impedance input (with reduced input capacitance) and converts signal levels, for example, from CMOS to current mode logic (CML). Driving four sets of input lines from each of the second stage input buffers 22 reduces the number of point cells 23 loading each input by a factor of four (only nine point cells 23 on each second stage buffer 22). Groups of multiple point cells are provided to first stage multiplexers 24 to allow the associated data streams to be directed to selected output ports. The capacitance load on each point cell 23 (which may be simply resistively loaded CML buffers) is reduced by collecting five first stage multiplexers 24 for each second stage multiplexer 25 such that each first stage multiplexer collects eight inputs. The second stage multiplexer 25 also acts as an output buffer and provides signal level conversion; for example, from CML to full swing CMOS.
Passive inductors have been used to increase the speed of these circuits by resonating out the effects of parasitic capacitances, an effect referred to as shunt peaking. The basic elements of a shunt peaked amplifier are shown in FIG. 3. This is a typical common source amplifier with a peaking inductance 304 placed in series with the drain load resistance 303. The bandwidth of such a circuit is a function of the values of the output capacitance 302, load resistance 303, and peaking inductance 304. As frequency increases, the decreasing reactance of the output capacitance 302 is offset by a corresponding increase in the reactance of the added peaking inductance 304. Thus, the overall output impedance remains relatively flat over a much broader frequency range than in a circuit without the peaking inductance 304. But in integrated circuits applications, use of passive inductors is undesirably area-intensive, especially if low power is desired.